Divider circuits are commonly used in integrated circuit devices to provide clock signals having a desired frequency. For example, clock generation integrated circuits (ICs) may use divider circuits to generate lower-frequency clock signals from a higher frequency periodic signal generated by a crystal oscillator or a resonant tank oscillator. Such clock generator ICs may be used in a wide variety of computing and telecommunications applications.
In many integrated circuit applications, it may be desirable to provide variable dividers that can be user-programmed to produce signals of various frequencies. It is generally desirable that a variable divider be able to operate from a relatively high frequency input clock signal to allow the divider circuit to provide relatively high output resolution. However, maintaining high resolution while providing a large division factor range may be difficult.
Divider circuits for clock signal generation commonly use chains of synchronous logic circuits (e.g., flip-flops) to divide the input clock signal down to a desired frequency. Such circuitry may consume an undesirable amount of space and power. Generally, the more a high frequency clock is divided by such a circuit, the more power is dissipated.